In recent years, to take advantage of low costs of CMOS, SOCs (System On Chip) were increasingly produced which mixed digital and analog circuits on one chip. In contrast, various information appliances were introduced to the market in recent years, and semiconductor integrated circuit devices, particularly LSIs, used for such appliances are developed. Since such SOCs became significantly large-scaled, there are strong demands on them for higher performance, more multifunctionality, miniaturization, and lower power consumption. The production processes are thus on a steady path of microfabrication.
In such a trend, D/A converters are used in various electronic devices for the purposes including control systems, display systems, video systems, audio systems, and communication systems. Although current steering D/A converters are essential which enable a high speed operation in LSIs for video and communication, the power voltage is low due to power reduction. Even in such a case however, there is a strong demand for securing a wide output voltage range because of the system demands and consideration for noise immunity.
Conventional techniques in the fields include the following, for example. FIGS. 5 and 6 are block diagrams of conventional current switch circuits. FIG. 5 of a prior art shows a circuit structure of a known current switch circuit. FIG. 6 shows a circuit structure of a conventional current switch circuit described in Patent Document 1 to solve the problem of FIG. 5.
A current switch circuit 2 shown in FIG. 5 includes a current source 21 and a differential switch 22. The current source 21 includes low voltage withstanding P channel type MOS transistors Tr211 and Tr212 each having a thin gate insulating film for operation at a low power voltage. The source terminal of the transistor 211 is connected to a first power potential VDD (in this section, VDD=1.8 V), and the drain terminal is connected to the source terminal of the transistor Tr212, and stabilized bias voltage Vbias1 is applied to the gate terminal. The drain terminal of the transistor Tr212 is connected to a node N10, and stabilized bias voltage Vbias2 is applied to the gate terminal. The substrate terminals of the two transistors Tr211 and Tr212 are connected to the first power potential VDD. Threshold voltage Vth of the low voltage withstanding transistor is set at approximately 0.3 V.
The differential switch 22 includes P channel type MOS transistors Tr221 and Tr222 each having the same low gate-withstanding voltage as that of the transistors of the current source 21. The source terminal of the transistor Tr221 is connected to the node N10, the drain terminal is connected to a non-inverting output terminal DAOUT10, and a positive phase digital signal outputted from a driving unit 20 is applied to the gate terminal of Tr221. In contrast, the source terminal of the transistor Tr222 is connected to the node N10, the drain terminal is connected to an inverting output terminal NDAOUT10, and a negative phase digital signal outputted from the driving unit 20 is applied to the gate terminal. The substrate terminals of the two transistors Tr221 and Tr222 are connected to the first power potential VDD.
Output load resistors R10 and R11 generate, as output current Iout of the current source 21 comes in, a positive phase output voltage at the non-inverting output terminal DAOUT10 and a negative phase output voltage at the inverting output terminal NDAOUT10 respectively, in which these output voltages are obtained from the current value of output current Iout and the resistance values of the output load resistors RIO and R11.
In a case that the D/A converter includes a plurality of current switch circuits 2, to maintain the linearity of the output signal of the D/A converter, i.e. not to deteriorate the SFDR (Spurious Free Dynamic Range), it is necessary to maintain the linearity of the output signals of the differential switches 22. In order to maintain the linearity of the output signals of the differential switches 22, it is necessary that the transistors Tr221 and Tr222 included in each differential switch 22 are operated in the saturation regions.
In the saturation regions of the transistors Tr221 and Tr222 shown in FIG. 5, gate-source voltage Vgs for each transistor is expressed as the following formula:|Vgs|=|Vth|+√{square root over (|Id|/(μCox/2·W/L)}  (1),wherein Id denotes the drain current, μ denotes the hole mobility, Cox denotes the gate capacitance per unit area, W denotes the gate width, and L denotes the gate length.
The condition for operating the transistors in the saturation regions is expressed as the following formula, by denoting the drain-source voltage as Vds:|Vds|≧|Vgs−Vth  (2).
The transistors Tr221 and Tr222 included in each differential switch 22 are turned on when the output signal from the driving unit is L (=VSS), and according to the formula (2) it is understood that the output voltage range of the D/A converter is from 0 to Vth.
As described above, in a case that a low voltage withstanding transistor is used to reduce the power voltage, the threshold voltage is approximately 0.3 V, and thus the output voltage range is limited to from 0 V to 0.3 V.
Maximum output amplitude Vomax of the D/A converter is determined according to the system demands, and a value of not less than 0.5V is often demanded.
FIG. 6 is a drawing that shows the technique of Patent Document 1. This is different from FIG. 5 in the point that the driving unit 20 includes an offset circuit 301 inside.
The current switch circuit 2 showed in FIG. 6 includes the current source 21 and the differential switch 22. The current source 21 includes the low voltage withstanding P channel type MOS transistors Tr211 and Tr212 for operation at a low power voltage. The source terminal of the transistor 211 is connected to the first power potential VDD, and the drain terminal is connected to the source terminal of the transistor Tr212, and stabilized voltage Vbias1 is applied to the gate terminal. The drain terminal of the other transistor Tr212 is connected to the node N10, and stabilized voltage Vbias2 is applied to the gate terminal. The substrate terminals of the two transistors Tr211 and Tr212 are connected to the first power potential VDD.
In FIG. 6, the differential switch 22 includes low voltage withstanding P channel type MOS transistors Tr221 and Tr222. The source terminal of the transistor Tr221 is connected to the node N10, the drain terminal is connected to a non-inverting output terminal DAOUT10, and a positive phase digital signal outputted from a driving unit 30 is applied to the gate terminal of Tr221. The source terminal of the other transistor Tr222 is connected to the node N10, the drain terminal is connected to the inverting output terminal NDAOUT10, and a negative phase digital signal outputted from the driving unit 30 is applied to the gate terminal. The substrate terminals of the two transistors Tr221 and Tr222 are connected to the first power potential VDD.
The output load resistors R10 and R11 generate, as output current Iout of the current source circuit 21 comes in, a positive phase output voltage at the non-inverting output terminal DAOUT10 and a negative phase output voltage at the inverting output terminal NDAOUT10 respectively, in which these output voltages are obtained from the current value of output current Iout and the resistance values of the output load resistors R10 and R11.
According to digital signal Din inputted at a first stage of the driving unit 30, a differential signal of L (=VSS) or H (=VDD) is generated. The offset circuit 301 included inside the driving unit 30 outputs differential signals DATA and NDATA with given offset voltages V1 and V2 (L=VSS+V1, H=VDD−V2) to the gate terminals of the transistors Tr221 and Tr222 included in the differential switch 22.
As described above, to maintain the linearity of the output signal of the D/A converter including the current switch circuit 2, it is necessary that the transistors Tr221 and Tr222 included in the differential switch 22 of the current switch circuit 2 are operated in the saturation regions and to fulfil Formula (2) above:|Vds|≧|Vgs−Vth|  (2).
The offset circuit 301 in the driving unit 30 determines the voltage, as VSS+V1, to be applied to the gate terminals during operation of the transistors Tr221 and Tr222 included in the differential switch circuit 22, and as a result, the output voltage range according to Formula (2) above is from 0 to Vth+V1.
Consequently, this output voltage range is from 0 to V1+Vth, and thus it is larger than the output voltage range of from 0 to Vth for the case of FIG. 5 by the amount of offset voltage V1. The technique of Patent Document 1 provided with the offset circuit 301 shown in FIG. 6 achieves a wider output voltage range by controlling gate-source voltage Vgs at a small value in Formula (2) above.
Patent Document 1: JP 2005-72794 A